Wafer-level packaging (WLP) packages an integrated circuit (IC) at wafer level. WLP is essentially a true chip scale package (CSP) technology, because the resulting package is practically the same size as the die. In a typical wafer level chip scale packaging (WLCSP), copper (Cu) posts are used to enhance the robustness for fine pitch or large die WLP. In general, a Cu post WLCSP process requires three or four lithographic masks. In the case of three-mask process, the photolithographic processes are used for forming a first polymer insulating layer, a redistribution line (RDL) and an under-bump metallurgy (UBM)/copper post respectively. In the case of four-mask process, the photolithographic processes are used for forming a first polymer insulating layer, a RDL, a second polymer insulating layer and a UBM/copper post respectively. Photolithographic operations, along with the costs to produce a photomask, are a significant portion of semiconductor manufacturing costs. Improvements in methods and structure of WLCSP having Cu post continue to be sought.